Validating Word-oriented Processors for Bit-level Permutations and Multi-word Operations in Pervasive Secure Computing Paradigms

Pervasive secure computing paradigms in the publicly interconnected world pose new challenges in the architecture of future general-purpose processors. These paradigms include safer communications, storage and execution. Basic security functions like confidentiality, data integrity and user authentication can be achieved by symmetric-key, hash and public-key cryptography algorithms, respectively. In analyzing these classes of algorithms, we identify two categories of operations not common in previous general-purpose workloads: bit operations within a word and multi-word operations. We describe where both types of operations are needed. Both challenge the basic word orientation of processors. We address both challenges in this paper. First, we show how difficult bit-level operations, namely arbitrary bit permutations within a word, can be achieved in just 1 or 2 cycles. This improves upon the O(n) instructions needed to achieve any one of n! permutations of n bits in existing RISC processors; it also improves upon recent work that achieves this in O(log(n)) instructions. This paper contributes two new architectural solutions, one with only micro-architecture changes, and another with ISA support as well. Slightly enhanced 4-way and 2-way superscalar microprocessors can achieve arbitrary 64-bit permutations in 1 or 2 cycles. The second challenge can be described as instructions that need more than two word-sized operands and/or produce more than one word-sized result. This is true in public-key algorithms where the key size and operands require multiple n-bit words per operand. It is also true in symmetric-key algorithms where, for example, the number of control bits needed to specify one of n! permutations exceeds the word-size of n bits. This paper shows how the second challenge can also be met by a generalization of our solutions to the first challenge. This validates current word-oriented processors while still achieving superior bitlevel and multi-word operations needed by emerging secure computing paradigms.